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1 HI-7159A microprocessor-compatible, 5- 1 / 2 digit a/d converter the intersil HI-7159A is a monolithic a/d converter that uses a unique dual slope technique which allows it to resolve input changes as small as 1 part in 200,000 (10 v) without the use of critical external components. its digital autozeroing feature virtually eliminates zero drift over temperature. the device is fabricated in intersil?proprietary low noise bimos process, resulting in exceptional linearity and noise performance. the HI-7159As resolution can be switched between a high resolution 200,000 count (5 1 / 2 digit) mode, and a high speed 20,000 count (4 1 / 2 digit) mode without any hardware modifications. in the 4 1 / 2 digit uncompensated mode, speeds of 60 conversions per second can be achieved. the HI-7159A is designed to be easily interfaced with most microprocessors through either of its three serial and one parallel interface modes. in the serial modes, any one of four common baud rates is available. features 200,000 count a/d converter 2v full scale reading with 10 v resolution 15 conversions per second in 5 1 / 2 digit mode 60 conversions per second in 4 1 / 2 digit mode serial or parallel interface modes four selectable baud rates differential analog input differential reference input digital autozero applications weigh scales part counting scales laboratory instruments process control/monitoring energy management seismic monitoring ordering information part number temp. range ( o c) package pkg. no. hi3-7159a-5 0 to 70 28 ld pdip e28.6 pinout HI-7159A (pdip) top view functional block diagram v cc int out int in buf out c ref- c ref- c ref+ c ref+ v ref hi v ref lo a gnd v in hi v in lo v ee sel d gnd p7/brs1 p6/brs0 p5/sad3 p3/sad1 p1/sms1 p0/sms0 cs/sad4 wr/txd rd/rxd x tal p4/sad2 p2/sad0 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 guard guard + + + buffer integrator comparator analog switches control section and latches analog state machine uart bus interface unit i/o ports sel 8 bit bus a gnd v ee v cc x tal d gnd c ref cs wr rd r int c int v in lo v in hi v ref lo v ref hi - - - data sheet january 1999 file number 2936.4 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | copyright intersil corporation 1999
2 absolute maximum ratings thermal information supply voltage v cc to gnd (a gnd /d gnd ) . . . . . . . . . . . . . . -0.3v < v cc < +6v v ee to gnd (a gnd /d gnd ) . . . . . . . . . . . . . . +0.3v < v cc < -6v digital pins, (pins 15 - 28) . . . . . . . . d gnd -0.3v < v d HI-7159A
3 dc electrical speci?ations test conditions: v cc = +5v, v ee = -5v, d gnd =0v,a gnd =0v,v ref hi = +1.00000v, v ref lo =a gnd , f clock = 2.40mhz, r int = 400k ? , c int = 0.01 f, t a = 25 o c, v in lo = a gnd , c ref = 1.0 f, 5 1 / 2 digit compensated mode, unless otherwise speci?d parameter test conditions min typ max units input low voltage, v il pins 15-25, 28 - - 0.8 v input high voltage, v ih pins 15-25, 28 2.0 - - v output low voltage, v ol pins 16, 18-25, i ol = 1.6ma - - 0.4 v output high voltage, v oh pins 16, 18-25, i oh = -400 a 2.4 - - v three-state leakage current, pins 18-25, i ol all digital drivers in high impedance state, parallel mode. cs = v cc , v in = 0v, v cc -- 10 a leakage, pins 15-17, 28, i in v in = 0v, v cc -- 1 a input capacitance, c in pins 15, 17-25, 28 - 5 - pf pin 16 - 10 - pf input pullup current (pins 18-25), i pu pins 18-25 at d gnd sel = d gnd (serial modes) --5- a ac electrical speci?ations t a = 0 o c to 75 o c; test conditions: v cc = +4.75v, v ee = -5.00v (note 8), d gnd = 0v, a gnd = 0v, v in lo =a gnd , v ref hi = +1.00000v, v ref lo = a gnd , f clock = 2.40mhz, r int = 400k ? , c int = 0.01 f, v il =0v, v ih = 4v, v ol =v oh = 1.5v, t r = t f < 10ns, 5 1 / 2 digit compensated mode, unless otherwise specified parameter test conditions min typ max units cs setup/hold of wr, t 1 0- -ns wr setup of data in, t 2 50 - - ns wr pulse width, t 3 150 - - ns data hold after wr, t 4 20 - - ns cs setup/hold of rd, t 5 (note 7) 25 - - ns rd to data out, t 6 c l = 50pf, v o = 1.5v - - 100 ns rd to hi-z state, t 7 - - 70 ns wr to rd, wr to wr, t a (note 7) 5/f clock --s rd to wr, t b (note 7) 200 - - ns rxd setup of data in, t c (note 7) 60 - - ns data hold after ext clk, t d 40 - - ns ext clk to data out, t e - - 300 ns cs setup of txd, t f 100 - - ns notes: 6. all typical values have been characterized but are not production tested. 7. not production tested, guaranteed by design and characterization. 8. all ac characteristics are guaranteed for v cc = +5v 15%, v ee = -5v 15%, over t a = 0 o c to 75 o c. HI-7159A
4 timing waveforms figure 1a. write figure 1b. write to read cycle figure 1c. write to write cycle figure 1d. read figure 1e. read to write cycle figure 1. parallel mode timing figure 2a. serial mode 0 timing note: all input timing shown is de?ed at 50% points. figure 2b. serial mode timing wr cs p0 - p7 data in t 1 t 2 t 3 t 4 t 1 wr rd t a wr t a cs rd t 7 p0 - p7 data out t 5 t 5 t 6 rd wr t b rxd/txd d0 d1 d2 d3 d4 d5 d6 d7 d1 d2 d3 d4 d5 d6 d7 rxd/txd clk (HI-7159A transmitting) (HI-7159A receiving) d0 t c t d t e (pin 15) (pin 16) (pin 16) cs txd or rxd parity stop start d0 d1 d2 d3 d4 d5 d6 d7 (serial mode 1) 0123 456789 10 11 12 13 14 15 data clock bit detector sample time t f HI-7159A
5 pin descriptions pin symbol description 1v cc positive 5v power supply for analog and digital sections. 2 int out integrator output; external component terminal. 3 int in integrator input; external component terminal. 4 buf out v in hi voltage buffer output; external component terminal. 5c ref - guard reference capacitor guard ring terminal (negative). 6c ref - reference capacitor negative terminal. 7c ref + reference capacitor positive terminal. 8c ref + guard reference capacitor guard ring terminal (positive). 9v ref hi positive reference input terminal. 10 v ref lo negative reference input terminal. 11 a gnd analog ground (0v). 12 v in hi positive analog input voltage terminal. 13 v in lo negative analog input voltage terminal. 14 v ee negative 5v power supply for analog section. 15 rd/rxd parallel read; serial receive (modes 1 and 2), serial clock (mode 0). 16 wr/txd parallel write; serial transmit (modes 1 and 2), serial receive/transmit (mode 0). 17 cs/sad4 chip select (parallel and serial modes 0 and 1), serial address bit 4 (mode 2). 18 p0/sms0 parallel i/o port (p0); serial mode select pin. 19 p1/sms1 parallel i/o port (p1); serial mode select pin. 20 p2/sad0 parallel i/o port (p2); serial address bit 0. 21 p3/sad1 parallel i/o port (p3); serial address bit 1. 22 p4/sad2 parallel i/o port (p4); serial address bit 2. 23 p5/sad3 parallel i/o port (p5); serial address bit 3. 24 p6/brs0 parallel i/o port (p6); serial baud rate select. 25 p7/brs1 parallel i/o port (p7); serial baud rate select. 26 d gnd digital ground (0v). 27 x ta l oscillator out; crystal connection pin (other crystal pin connected to v cc ). 28 sel select pin for parallel or serial operation. parallel sel = 1 serial modes sel = 0 mode sms0 sms1 serial mode 0 0 0 serial mode 1 0 1 serial mode 2 1 0 reserved 1 1 baud rate brs0 brs1 300 0 0 1200 0 1 9600 1 0 19200 1 1 HI-7159A
6 theory of operation the HI-7159A attains its 5 1 / 2 digit resolution through the use of multiple integrations per conversion, creating an effective integrator swing greater than the supply rails, and a successive integration technique used to measure the residue on the integrator capacitor to 5 1 / 2 digit accuracy. in the 5 1 / 2 digit mode, the input voltage is integrated and reference de-integrated four times. this results in a count with the same effective resolution as a single integration with four times the integrator swing amplitude. in this manner effective integrator swings of 12v or greater can be achieved with 5v supplies. the four integrations are spaced so that common- mode signals whose frequency is an integer multiple of f crystal /40,000 are rejected. in the 4 1 / 2 digit mode, only one input integration is performed, thus the minimum frequency for common-mode rejection becomes f crystal /10,000. these ?st four integrations measure the input voltage to an resolution of 3 1 / 2 digits, or 1mv/count. to achieve 5 1 / 2 digit accuracy (10 v/count), the error voltage remaining on the integrator capacitor (representing the overshoot of the integrator due to comparator delay and clock quantization) must be measured and subtracted from the 3 1 / 2 digit result. this is accomplished by multiplying the residue by a factor of 10, then integrating and reference de-integrating the error. this error is subtracted from the 3 1 / 2 digit result, yielding a 4 1 / 2 digit accurate result. the error remaining from this step is then multiplied by 10 and subtracted, and the process is repeated a third time to achieve an internal accuracy of 6 1 / 2 digits. this result is rounded to 5 1 / 2 digits and transferred to the holding register, where it can be accessed by the user through one of the three communications modes. conversion types the HI-7159A offers the user a choice of three different conversion types. they are: (1) the converters internal offset voltage, measured by internally connecting v in hi and v in lo to a gnd and doing a conversion (error only mode); (2) the input voltage (v in hi minus v in lo ) including the converters internal offset (uncompensated mode); and (3) the input voltage including internal offset errors, minus the internal offset errors (compensated mode). this last measurement is a digital subtraction of an error only conversion from an uncompensated conversion, and is the default conversion type. since a compensated conversion consists of two conversions, it takes twice as long to perform as the first two types. under some conditions, it may be desirable to increase the conversion rate without loss of resolution or accuracy. since the short term drift of the internal offset error is slight when temperature is controlled, it is not always necessary to convert the error voltage once for every input voltage conversion. it is possible for the host processor to do an error conversion periodically, store the result, and subtract the error from a stream of uncompensated input conversions with its own internal alu. in this way the conversion rate can be effectively doubled. communication modes the HI-7159A a/d converter receives instructions from and transmits data to the user host processor through one of four communication modes. the modes are: parallel microprocessor (parallel); synchronous serial (serial mode 0); serial non-addressed (serial mode 1); and serial addressed (serial mode 2). the mode is determined by the states of the sel, sms0, and sms1 pins as shown in table 1. the parallel mode allows the converter to be attached directly to a microprocessor data bus. data is read and written to the device under control of the microprocessors rd, wr and cs signals. serial mode 0 permits high speed serial data transfer at up to 1 megabits/s. serial mode 1 reads and writes industry standard serial data packets consisting of 1 start bit, 8 data bits, 1 parity bit (even), and 1 stop bit, at one of 4 hardware selectable baud rates. serial mode 2 is identical to serial mode 1 with the addition of addressing capabilities which allow up to 32 HI-7159As to share the same serial line, with each assigned a unique address. all four modes follow the same interface protocol: a request or a command is sent from the host to the HI-7159A, and the converter responds with the requested data and, in the case of a command, begins a new conversion. parallel mode operation the parallel communication mode (figure 3) is selected when sel (pin 28) is high. pins 18-25 become the eight bidirectional data bits, p0-p7. pins 15, 16, and 17 respectively become read ( rd), write ( wr), and chip select ( cs). timing parameters for the parallel mode are shown in figure 1. serial mode 0 serial mode 0 is the high speed synchronous serial interface, directly compatible with the mcs-51 series of microcontrollers. it is enabled by tying sel (pin 28), sms0 (pin 18) and sms1 (pin 19) low (figure 4a). pin 16 is the bidirectional serial data path, and pin 15 is the data clock input. data sent to the HI-7159A is latched on the rising edge of the serial clock. see figure 2a for detailed timing information. only 8 data bits are used in this mode - no start, stop, or parity bits are transmitted or received. cs must either be tied to d gnd or pulled low to access the device. the sad0 - sad3 and brs0 - brs1 pins are unused in this mode and should be tied high. table 1. communication mode selection communication mode sel pin 28 sm s0 pin 18 sm s1 pin 19 parallel v cc n/a n/a serial 0 d gnd d gnd d gnd serial 1 d gnd d gnd v cc serial 2 d gnd v cc d gnd HI-7159A
7 serial mode 1 serial mode 1 is selected by tying sms0 (pin 18) low, sms1 (pin 19) high, and sel (pin 28) low (figure 4b). in this mode the HI-7159A interface emulates a uart, reading and writing data in serial data packets of 1 start bit, 8 data bits, 1 parity bit (even), and 1 stop bit. the baud rate is determined by the state of brs0 and brs1 (pins 24 and 25) as shown in table 2. pin 15 becomes the serial receiver pin (rxd) and pin 16 the serial transmitter pin (txd). cs (pin 17) remains a chip select and must either be tied to d gnd or pulled low (see figure 2b) to access the device. sad0-sad3 (pins 20-23) are unused in this mode and should be tied high. design hints for operating in the parallel mode 1. always read the status byte twice to make sure that it is cleared. 2. make sure the status byte is cleared before issuing a command to change modes. 3. read each digit pair ?e times before reading the next byte to ensure that the output data is correct. 4. use a watchdog timer to monitor conversion time. if conversion time is either too long or too short, reissue the conversion command. table 2. baud rate selection for modes 1 and 2 brs0 pin 24 brs1 pin 25 baud rate (f xtal = 2.4576mhz) baud rate vs f xtal d gnd d gnd 300 f xtal /8192 d gnd v cc 1200 f xtal /2048 v cc d gnd 9600 f xtal /256 v cc v cc 19200 f xtal /128 +5v cs 15 rd 14 28 sel 1 27 16 17 address decoder 26 25 d7 18 d0 rd d7 d0 p x tal d gnd address bus data bus v ee v cc wr wr -5v hi- 7159a figure 3. parallel mode configuration figure 4a. serial mode 0 figure 4b. serial mode 1 figure 4c. serial mode 2 figure 4. serial mode configurations +5v cs 15 14 1 27 16 26 18 17 28 clk rxd/txd clk rxd/txd sm0 sel 8051 19 sm1 10 11 v ee v cc d gnd HI-7159A -5v 20-25 +5v p x tal x tal +5v txd rxd rxd txd sm0 +5v sm1 brs0 brs1 +5v 20k 20k x tal x tal v cc v ee cs sel d gnd -5v +5v uart/ p 15 14 1 27 16 19 18 24 25 26 17 28 20 - 23 HI-7159A +5v 15 14 1 27 16 26 19 18 28 txd rxd rxd txd 24 25 brs0 brs1 +5v sel uart/ p 20k 20k sm1 +5v sm0 address select 20 21 22 23 17 v cc v ee d gnd HI-7159A -5v to up to 31 additional HI-7159As x tal x tal HI-7159A
8 serial mode 2 serial mode 2 is selected by tying sel (pin 28) low, sms0 (pin 18) high, and sms1 (pin 19) low, as shown in figure 4c. this mode of operation is identical to serial mode 1, except that each device now has one of 32 unique addresses determined by the state of pins 20-23 and 17, as shown in table 3. this allows multiple HI-7159As to be attached to the same pair of serial lines. when the microprocessor sends out an address byte (table 4) that matches one of the HI-7159As hardwired addresses, that particular HI-7159A is selected for all further i/o until another address byte with a different address is transmitted. reading the HI-7159A despite the wide variety of interface options available on the HI-7159A, the procedure for communicating with it is essentially the same in all four modes. (serial mode 2 differs from the rest in two respects: the chip to be communicated with must ?st be sent an address byte to select it, and the digit bytes are sent one by one, for a total of six bytes, instead of in pairs.) there are two types of bytes that can be sent to the converter, commands and requests. a command byte (table 5) sets the parameters of and initiates a conversion. those parameters are: continuity of the conversion (single or continuous), resolution (5 1 / 2 or 4 1 / 2 digits), and type of conversion (compensated, uncompensated, or error only). bit d0 = 0 indicates that this is a command byte and a new conversion(s) should be started. a request byte (table 6) asks for either the status of the converter or the result of a conversion. all bits of a request should be set to 0 except d3, d2, and d0. d3 and d2 determine the type of request (status or digit pair), and d0 = 1 indicates to the HI-7159A that this is a request byte. serial mode 2 uses a slightly modi?d request byte, shown in table 7, allowing it to individually select each of the six digit bytes. upon receipt of a request, the HI-7159A will respond with either a status or a digit byte. the status byte (table 8) returns the current state of the converter. bit d6 = 1 indicates that a new conversion has been completed since the last time the status byte was read. bit d6 is cleared after it is read. bit d4 shows the current continuity (single or continuous). bit d3 indicates the resolution (5 1 / 2 or 4 1 / 2 digits) of the conversion, and bits d2 and d1 indicate the type (compensated, uncompensated, or error only). bit d0 = 0 indicates that there was no parity error detected in the last request byte. the three digit bytes (table 9) each contain two nibbles representing two digits of the conversion. the sixth nibble contains the msd (most signi?ant digit), polarity (1 = positive) and overrange (1 = overrange) information. in serial mode 2 the digits (table 10) are requested and received individually, so a total of six requests and six reads is necessary to obtain all 5 1 / 2 digits. table 3. hardware address selection for mode 2 pin 17 pin 23 pin 22 pin 21 pin 20 b4 (msb) b3 b2 b1 b0 (lsb) table 4. serial mode 2 address byte format (sent to HI-7159A) address bit (reserved) (msb) (lsb) d7 d6 d5 d4 d3 d2 d1 d0 1 00b4b3b2b1b0 table 5. command byte format (sent to HI-7159A) (reserved) continuity resolution conversion type command bit d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 single 0 5 1 / 2 1 comp 1 1 0 continuous 1 4 1 / 2 0 uncomp 1 0 error only 0 1 table 6. request byte format, parallel and serial mode 1 (sent to HI-7159A) (reserved) byte request (reserved) request bit d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 digit pair 0, 1 0 0 0 1 digit pair 2, 3 0 1 digit pair 4, 5 1 0 converter status 1 1 HI-7159A
9 single conversion mode the suggested algorithm for reading the HI-7159A in its single conversion mode of operation is shown in figure 5. essentially it consists of initiating a conversion, waiting until the conversion is complete, and then reading the results. since no further conversions take place, the data may be read out at any time and at any speed. this is the most straightforward method of reading the HI-7159A. continuous conversion mode once a command byte is sent to the HI-7159A initiating the continuous conversion mode, the output data registers will be updated continuously after every conversion. this makes obtaining a valid reading more difficult, since the possibility exists that the current data could be overwritten by a new conversion before all the digit bytes are read. to prevent this, the status byte should be read before and after the data is read from the converter, to ensure that the converter has not updated during the reads. this is demonstrated in figure 6. table 7. request byte format, serial mode 2 (sent to HI-7159A) (reserved) byte request request bit d7 d6 d5 d4 d3 d2 d1 d0 0000 digit 0 0 0 0 1 digit 1 0 0 1 digit 2 0 1 0 digit 3 0 1 1 digit 4 1 0 0 digit 5 1 0 1 converter status 1 1 0 table 8. status byte format (received from HI-7159A) ( ? ) converter update status ( ? ) continuity resolution conversion type parity error d7 d6 d5 d4 d3 d2 d1 d0 0 no update 0 0 single 0 5 1 / 2 1 comp 1 1 no 0 updated 1 continuous 1 4 1 / 2 0 uncomp 1 0 yes 1 error 0 1 ( ? = reserved) table 9. digit byte format, parallel and serial mode 1 (received from HI-7159A) digit byte d7 d6 d5 d4 d3 d2 d1 d0 digit pair 0, 1 msb1 lsb1 msb0 lsb0 digit pair 2, 3 msb3 lsb3 msb2 lsb2 digit pair 4, 5 polarity (1 = pos) overrange (1 = or) msb5 lsb5 msb4 lsb4 table 10. digit byte format, serial mode 2 (received from HI-7159A) digit byte d7 d6 d5 d4 d3 d2 d1 d0 digits 0 - 4 0011msb lsb digit 5 0011 polarity (1 = pos) overrange (1 = or) msb lsb HI-7159A
10 due to the wide range of baud rates available in the serial modes, some of the lower baud rates will take longer to transfer the output data than it takes to perform a conversion. in these cases the continuous mode should not be used. table 11 shows the percentage of the total conversion time that it takes to read all the data from the converter for the two serial modes. these are best case numbers, assuming that the bytes are transmitted and received end-to-end. an asterisk indicates that it is impossible to get all the data out within one conversion. percentages in the 20-50% range indicate that it is possible to get valid data out with very tight code. in all cases the status byte should be checked before and after the reading to ensure data integrity. crystal oscillator the HI-7159A uses a single pin crystal oscillator design (figure 7). the crystal is connected between pin 27 and v cc ; no load capacitors or other components are necessary. the user has a choice of crystal frequencies: 2.4576mhz or 2.4mhz. an off-the-shelf 2.4576mhz crystal works well and provides baud rates of exactly 19.2k, 9600, 1200, and 300. however its total integration period will be 16.28ms, or 0.39ms shorter than a 60hz cycle. this effectively reduces the normal mode ac rejection. a 2.4mhz crystal results in an integration period of 16.67ms, exactly the length of one 60hz ac cycle. normal mode ac rejection is greatest at this frequency. at 2.4mhz, however, the baud rates will be off by -2.34%. this error is not large enough to cause any errors with most peripherals, and only applies to operation in serial modes 1 and 2. communication in serial mode 0 and the parallel mode is independent of the crystal frequency. for this mode a 2.4mhz crystal is recommended. while the oscillator was designed to operate at 2mhz - 2.5mhz, the HI-7159A itself will operate reliably down to less than 600khz when driven with an external clock. bene?s at lower clock frequencies include reduced rollover error (gain error for negative input voltages) and lower noise. the baud rates mentioned throughout this data sheet correspond to a crystal frequency of 2.4576mhz. at 1.2mhz, the actual baud rates will be half the speed they were at 2.4mhz, i.e., 9600, 4800, 600 and 150 baud. at 600khz they will be one-fourth. send command byte (initiate single conversion) conversion result is valid d6 = 1? get status byte get digit bytes no yes figure 5. reading the HI-7159A in the single conversion mode get status byte get digit bytes d6 = 0? conversion result is valid get status byte yes no conversion result may be invalid: discard result no yes d6 = 1? figure 6. reading the HI-7159A in the continuous conversion mode table 11. serial modes 1 / 2 baud rate conversion type 5 1 / 2 comp 5 1 / 2 uncomp 4 1 / 2 comp 4 1 / 2 uncomp 300 * / ** / ** / ** / * 1200 54%/ ** / ** / ** / * 9600 7%/13% 14%/25% 27%/50% 54%/ * 19200 4%/7% 7%/13% 14%/25% 27%/50% +5v 1 27 v cc x tal crystal (2mhz to 2.5mhz) HI-7159A figure 7. single-pin oscillator HI-7159A
11 it may also be possible to directly program the hosts serial hardware for operation at nonstandard baud rates, allowing HI-7159A operation at any arbitrary frequency. for example: 50hz ac rejection requires a 2mhz clock. at this frequency the ?600?baud rate becomes 7812.5 baud. the hosts uart must be programmed with the proper divider to operate at this baud rate. the data clock (see figure 2) is de?ed as 16 times the baud rate, so the data clock of this con?uration would be 125khz. the data clock can also be determined by dividing the oscillator (clock) frequency by the correct divider from table 12. the following equation determines the divider needed to operate the HI-7159A at any given crystal frequency: once determined, the new divider must be written directly to the hosts uart. most pc compatibles use an 8250 uart with a 1.8432mhz crystal, so the proper divider for the 2mhz example given above would be 15. again, these considerations apply only to serial modes 1 and 2. parallel and serial mode 0 communication rates are independent of crystal frequency. conversion time the conversion time of the HI-7159A is a function of the crystal frequency and the type of conversion being made. the conversion times for f clock = 2.4mhz are shown in table 13. at other clock frequencies the times may be calculated from the following formula: where the constant c is determined from table 13. component selection three external passive components must be chosen for the HI-7159A: the integrating capacitor (c int ), the integrating resistor (r int ), and the reference capacitor (c ref ). they are chosen based on the crystal frequency, the reference voltage (v ref ), and the desired integrating current. figure 8 illustrates the analog components necessary for the HI-7159A to function. the reference capacitor and integrating components can either be selected from table 14, or calculated from the following equations. c ref acts as a voltage source at different times during a conversion. its value is determined by two considerations: it must be small enough to be fully charged from its discharged state at power-on; yet it also must be large enough to supply current to the circuit during conversion without significantly drooping from its initial value. for 2.4mhz operation, a 1 f capacitor is recommended. the equation for other frequencies is: the values of r int and c int are selected by choosing the maximum integration current and the maximum integrator output voltage swing. the maximum integration current and voltage swing occurs when v in = full scale = 2 x v ref . the recommended integration current for the HI-7159A is 5ma - 10ma. this will help determine the value of r int , since: where v in = v in hi - v in lo = 2 x v ref . table 12. crystal divider ratios baud rate selected crystal divider ?00 512 ?200 128 ?600 16 ?9200 8 table 13. conversion times conversion type 5 1 / 2 comp 5 1 / 2 uncomp 4 1 / 2 comp 4 1 / 2 uncomp f = 2.4mhz 133ms 66.7ms 33.3ms 16.7ms c 320,000 160,000 80,000 40,000 f clock 7159a () divider 7159a () -------------------------------------------- f crystal host uart () divider host uart () --------------------------------------------------------------- - data clock == t conv c f clock --------------------- = table 14. recommended component values vs clock frequency f clock r int c int c ref 2.4mhz 400k ? 0.01 f 1.0 f 1.2mhz 360k ? 0.022 f 2.2 f 600khz 330k ? 0.047 f 4.7 f note: c int must be a high quality polypropylene capacitor or performance may be degraded. +5v 27 1 v cc v ee 14 a gnd int out int in buf out d gnd r int c int c ref - c ref+ c ref c ref+ guard 2 3 4 5 6 7 8 9 12 13 11 10 26 reference capacitor guard rings d gnd a gnd v ref hi ref lo v in hi v in lo -5v HI-7159A c ref - guard figure 8. analog components and inputs x tal c ref 2.5 f clock --------------------- = i int v in r int ------------- so r int v in i int ---------- - , == HI-7159A
12 therefore values of r int should be between 200k ? and 400k ? . the exact value of r int may be altered to get the exact integrator swing desired after choosing a standard capacitor value for c int . the most critical component in any integrating a/d converter is the integrating capacitor, c int . for a converter of this resolution, it is imperative that this component perform as closely to an ideal capacitor as possible. any amount of leakage or dielectric absorption will manifest itself as linearity errors. for this reason c int must be a high quality polypropylene capacitor. use of any other type may degrade performance. the value of c int is determined by the magnitude of the desired maximum integrator output voltage swing as shown below: solving for c int yields: where v swing is the maximum output voltage swing of the integrator, v in is the full scale input voltage (v in hi -v in lo ) to the converter (equal to 2 x v ref ), and t int is the time in which v in is integrated. the best results are achieved when the maximum integrator output voltage is made as large as possible, yet still less than the nonlinear region in the vicinity of the power supply limit. a full scale output swing of about 3v provides the greatest accuracy and linearity. note: the integrator is auto-zeroed to the voltage at v in lo .if vin lo is negative with respect to a gnd , the integrator will have | v in lo | less headroom for positive input voltages (inputs where v in hi -v in lo > 0). if v in lo is positive with respect to a gnd , the inte- grator will have | v in lo | less headroom for negative input voltages (inputs where v in hi -v in lo < 0). in most applications v in lo is at or near a gnd and the above equations will be adequate. in applica- tions where v in lo may be more than 0.1v away from a gnd , it should be included in the integrator swing considerations. the follow- ing formula combines all the above considerations:. gain error adjustments while the HI-7159A has a very linear transfer characteristic in both the positive and negative directions, the slope of the line is slightly greater for negative inputs than for positive. this results in the transfer characteristic shown in figure 9. one end point of this curve, typically the positive side, can be adjusted to zero error by trimming the reference voltage. the other (negative) side will have a ?ed gain error. this error can be removed in software by multiplying all negative readings by a scale factor, determined by dividing the ideal full scale reading (-200,000 counts) by the actual full scale reading when v in = -2.00000v. c ref guard pins depending on the polarity of the input signal, either the negative or the positive terminal of the reference capacitor will be connected to a gnd to provide the correct polarity for reference deintegration. in systems where v ref lo is tied to analog ground, the reference capacitor is effectively shifted down by | v ref | for positive input voltages, and is not shifted at all for negative input voltages. this shift can cause some charge on the reference capacitor to be lost due to stray capacitance between the reference capacitor leads and ground traces or other fixed potentials on the board. the reference voltage will now be slightly smaller for positive inputs. this difference in reference voltages for positive and negative inputs appears as rollover error. the HI-7159A provides two guard ring outputs to minimize this effect. each guard ring output is a buffered version of the voltage at its respective c ref pin. if the traces going to the c ref pins and under c ref itself are surrounded by their corresponding guard rings, no charge will be lost as c ref is moved. figure 10 shows two slightly different patterns. the ?st one is for capacitors of symmetrical construction, the second is for capacitors with outside foils (one end of the capacitor is the entire outside. v swing v in () t int () r int () c int () ------------------------------------- = c int v in () t int () r int () v swing () ----------------------------------------------- = v in lo v in hi v in lo () 10 000 , () r int () c int () f osc () ----------------------------------------------------------------------- 3v 200,000 100,000 000,000 -100,000 -200,000 output count -2 input (v) -200,012 counts -1 0 1 2 figure 9. typical HI-7159A transfer characteristic guard c ref - (5) c ref - (6) c ref + (7) c ref + guard (8) guard (5) (6) (7) guard (8) hi -7159a hi -7159a figure 10. typical guard ring layout c ref - c ref - c ref + c ref + HI-7159A
13 die characteristics die dimensions: 5817 m x 3988 m metallization: type: sial thickness: 10k ? 1k ? passivation: type: psg/nitride thickness: 15k ? 1k ? metallization mask layout HI-7159A buf out int in int out v cc v cc sel x tal d gnd p7/brs1 p6/brs0 p5/sad3 p4/sad2 p3/sad1 p2/sad0 p1/sms1 p0/sms0 cs/sad4 wr/twd rd/rxd v ee v in lo v in hi a gnd v ref lo v ref hi c ref - c ref + c ref - guard c ref + guard HI-7159A
14 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site http://www.intersil.com sales of?e headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (321) 724-7000 fax: (321) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil (taiwan) ltd. 7f-6, no. 101 fu hsing north road taipei, taiwan republic of china tel: (886) 2 2716 9310 fax: (886) 2 2715 3029 HI-7159A dual-in-line plastic packages (pdip) notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the inch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?o series symbol list in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are measured with the package seated in jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be perpendic- ular to datum . 7. e b and e c are measured at the lead tips with the leads unconstrained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- c l e e a c e b e c -b- e1 index 1 2 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a1 -a- 0.010 (0.25) c a m bs e28.6 (jedec ms-001-bf issue d) 28 lead narrow body dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.250 - 6.35 4 a1 0.015 - 0.39 - 4 a2 0.125 0.195 3.18 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.030 0.070 0.77 1.77 8 c 0.008 0.015 0.204 0.381 - d 1.380 1.565 35.1 39.7 5 d1 0.005 - 0.13 - 5 e 0.600 0.625 15.24 15.87 6 e1 0.485 0.580 12.32 14.73 5 e 0.100 bsc 2.54 bsc - e a 0.600 bsc 15.24 bsc 6 e b - 0.700 - 17.78 7 l 0.115 0.200 2.93 5.08 4 n28 289 rev. 0 12/93

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